1. Technical Field
The invention generally relates to nonvolatile random access memory arrays, and more specifically to nonvolatile random access memory arrays that use nanotube articles having re-programmable resistance to provide unit cells that may be employed in integrated circuits.
2. Discussion of Related Art
Important characteristics for a memory cell for use in a commercial electronic device are having a low production cost, nonvolatility, high density, low power, and high speed. Conventional memory solutions include Read Only Memory (ROM), Programmable Read only Memory (PROM), Electrically Programmable Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM).
ROM has a relatively low cost but cannot be rewritten. PROM can be electrically programmed, but with only a single write cycle. EPROM has read cycles that are fast relative to ROM and PROM read cycles, but has relatively long erase times and is reliable for only a few iterative read/write cycles. EEPROM (or “Flash”) is inexpensive to produce and has low power consumption, but has long write cycles (ms) and low relative speed in comparison to DRAM or SRAM. Flash also has a finite number of read/write cycles, which leads to low long-term reliability. ROM, PROM, EPROM and EEPROM are all non-volatile, meaning that if power to the memory is interrupted, the memory will retain the information stored in the memory cells.
DRAM stores charge on transistor gates that act as capacitors. These capacitors must be electrically refreshed every few milliseconds to compensate for charge leakage. Also, a read operation discharges the capacitors, so the information must subsequently be rewritten to the memory. This complicates the system design, because separate circuitry must be included to “refresh” the memory contents both before the capacitors discharge, and after a read operation. SRAM does not need to be refreshed, and is fast relative to DRAM, but has lower density and is more expensive relative to DRAM. Both SRAM and DRAM are volatile, meaning that if power to the memory is interrupted, the memory cells will lose their stored information.
Consequently, existing commercially available technologies are generally either nonvolatile, but not randomly accessible and have a low density, high production cost, and a limited ability to allow multiple writes with high reliability of the circuit's function; or are volatile, and have complicated system design or have a low density. Some emerging technologies have attempted to address these shortcomings.
For example, magnetic RAM (MRAM) or ferromagnetic RAM (FRAM) have nonvolatile memory cells that are generated from the orientation of a magnetic or ferromagnetic region of material. MRAM utilizes a magnetoresistive memory element, which is based on either the anisotropic magnetoresistance or giant magnetoresistance of ferromagnetic materials. Both of these types of memory cells are nonvolatile, but have a relatively high resistance and low density. A different proposed magnetic memory cell, based upon magnetic tunnel junctions, has also been examined but has not led to large-scale commercialized MRAM devices. FRAM uses a circuit architecture similar to DRAM, but instead utilizes a thin film ferroelectric capacitor and an externally applied electric field. This capacitor is believed to retain its electrical polarization after removing the externally applied electric field, yielding a nonvolatile memory cell. However FRAM memory cells tend to be large, and are difficult to manufacture as large-scale integrated components. See U.S. Pat. Nos. 4,853,893; 4,888,630; 5,198,994.
Another emerging nonvolatile memory technology is phase change memory. This technology stores information by inducing a structural phase change in thin-film alloys, which incorporate elements such as selenium or tellurium. These alloys are believed to remain stable in both crystalline and amorphous states, allowing the formation of a bi-stable switch that functions as a nonvolatile memory cell. This technology, however, appears to operate at a slow speed, to be difficult to manufacture, has unknown reliability, and has not reached a state of commercialization. See U.S. Pat. Nos. 3,448,302; 4,845,533; 4,876,667; 6,044,008.
Wire crossbar memory has also been proposed. See U.S. Pat. Nos. 6,128,214; 6,159,620; and 6,198,655. These proposed memory cells utilize molecules to build bi-stable switches. Two wires (which can be metal or semiconductor depending on the particular implementation) are crossed, with a layer of one or more molecular compounds sandwiched between the wires at the junction. By controlling the sandwiched compound(s), e.g. by chemical assembly or by electrochemical oxidation/reduction reactions, the two wires are brought into or out of electrical contact with each other to generate a respective “on” or “off” state. This form of memory cell has the manufacturing limitation of requiring highly specialized wire junctions. It also may not retain nonvolatility or long-term reliability owing to the inherent instability found in redox processes, and the risk of degradation of the chemical compound(s).
Recently, memory devices have been proposed which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions that serve as memory cells. See WO 01/03208, “Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture;” and Thomas Rueckes et al., “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” Science, vol. 289, pp. 94-97, 7 Jul., 2000. Hereinafter these devices are called nanotube wire crossbar memories (NTWCMs). In these proposed devices, individual single-walled nanotube wires are suspended over other wires, defining memory cells. Electrical signals that are written to one or both wires cause them to physically attract or repel relative to one another. Each physical state (i.e., attracted or repelled wires) corresponds to an electrical state. Repelled wires form an open circuit junction. Attracted wires form a closed state, forming a rectified junction. When electrical power is removed from the junction, the wires retain their physical (and thus electrical) state, thereby forming a nonvolatile memory cell.
More recently proposed nanotube ribbon crossbar memory (NTRCM) devices offer the advantages of being non-volatile, having a low production cost per bit, a high density, fast random access, and low power consumption, and also having a high degree of tolerance to radiation. The memory offers competitive performance to and achieves a higher density than conventional SRAM, because it utilizes a two-device structure having an electromechanically responsive nanotube plus 3 array lines to control and read the memory cell state. The memory offers the relative advantages of having a non-destructive read-out (NDRO) operation, and nonvolatility.
U.S. Pat. No. 6,919,592 discloses, among other things, NTRCM-based electromechanical circuits, such as memory cells. These circuits include a structure having supports extending from a surface of a substrate, and electrically conductive traces in between. The supports suspend nanotube ribbons across the electrically conductive traces. Each ribbon comprises one or more nanotubes. For example, as disclosed in U.S. Pat. No. 6,919,592, a fabric of nanotubes (nanofabric) may be patterned into ribbons. Then the ribbons can be used as components to create nonvolatile electromechanical memory cells. The ribbon is electromechanically deflectable in response to electrical stimulus of control traces and/or the ribbon. The deflected physical state of the ribbon may be made to represent a corresponding information state. The deflected physical state has nonvolatile properties, meaning the ribbon retains its physical (and therefore informational) state even if power to the memory cell is removed. As explained in U.S. Pat. No. 6,911,682, three-trace architectures may be used for electromechanical memory cells, in which the two of the traces are electrodes to control the deflection of the ribbon.
The ribbons may be formed, for example, as disclosed in U.S. Pat. No. 6,919,592, by selectively removing material from a deposited or grown layer or matted fabric of nanotubes. To fabricate suspended nanotube ribbons, multiple masking steps may be used. Sacrificial layers may be fabricated both above and below the nanotube ribbons in the switching regions, where the ribbons will be suspended. The sacrificial layers may be subsequently removed in order to leave spaces above and below the ribbons, i.e. to suspend the ribbons.
An ideal memory device for at least some purposes is one that enables a simple, low cost integration for fabrication using existing bulk or SOI CMOS processes. Such a memory device could be fabricated with only one additional masking layer (or at most two additional masking layers) and a minimum number of additional process steps.